In brief: The world's leading semiconductor foundry, TSMC, isn't resting on its laurels. At its recent symposium for North American customers, the chipmaker unveiled ambitious roadmaps for both chip packaging and bleeding-edge optical interconnect technologies. These advancements could unleash a tidal wave of compute performance in the coming years.
Starting with the chip packaging tech, which TSMC has branded "CoWoS" (Chip-on-Wafer-on-Substrate), it's essentially an enhanced version of typical chiplet designs, where multiple smaller dies are integrated together into one package. But TSMC is taking it to incredible new levels of scale and complexity.
The current CoWoS iteration supports interposers (the silicon base layer) up to 3.3x the size of a typical photomask used in lithography. But by 2026, TSMC's "CoWoS_L" will bump that up to around 5.5x mask size, leaving room for larger logic chiplets and up to 12 stacks of HBM memory. And just a year later in 2027, CoWoS will scale up to a jaw-dropping 8x reticle size or more.
We're talking integrated packages spanning 6,864 mm2, significantly larger than a credit card. These CoWoS behemoths could incorporate four stacked logic chiplets alongside a dozen HBM4 memory stacks and extra I/O dies.
To give you a sense of the scale, Broadcom recently showed off a custom AI processor with two logic dies and 12 memory stacks. And that chip looked bigger than Nvidia's latest beefy accelerators, but it's still puny compared to what TSMC is prepping for 2027. In fact, the company expects its solutions to use up to a whopping 120x120mm substrate.
In the context of chip manufacturing, a larger substrate allows for more components to be integrated onto it, potentially enabling more powerful and complex electronic devices. But the monstrous scale also means they'll consume kilowatts of power and likely require exotic liquid cooling solutions. Nothing about this is excessive, though, considering how power-hungry generative AI is turning out to be. We're entering uncharted waters for semiconductor packaging here.
Speaking of uncharted waters, TSMC also revealed its "3D Optical Engine" strategy to integrate lightning-fast optical interconnects into its client designs. As bandwidth demands explode, copper traces simply won't cut it for bleeding-edge datacenter and HPC workloads. Optical links, leveraging integrated silicon photonics, offer vastly higher throughput and lower power.
TSMC's "COUPE" (Compact Universal Photonic Engine) co-packages electronics and photonics using advanced 3D stacking. Gen 1 plugs into standard optical ports at 1.6 Tbps - double what top-end Ethernet offers today. Gen 2 boosts that to 6.4 Tbps by integrating COUPE into TSMC's CoWoS packages alongside the processor. And the roadmap culminates with a CoWoS "COUPE Interposer" design hitting an astounding 12.8 Tbps of optical bandwidth.
Whether it's ungodly AI models, physics simulations, or just colossal datacenter workloads, the chipmaker seems convinced that "go big or go home" will reign supreme in the years ahead.